Reproduced from Commodore World Magazine issue 12, January 1996.
By Mark Fellows and Doug CottonEditA Sneak Preview of the SuperCPU
With the upcoming release of CMD's SuperCPU, there have been numerous calls, letters, and E-mail messages from users asking about this new product. What is it? What does it do? Where does it plug in? How will it affect the operation of your computer?
Hopefully, many of these questions will be answered by this exclusive preview of the product. It is important to note, however, that the SuperCPU is a work in progress, and that some of the details simply aren't available yet. As they become known, we'll endeavor to keep our readers informed, and up-to-date.
Let me also point out that CMD has already altered some of their plans for the SuperCPU product line. If you haven't yet read On The Horizon in this issue, CMD has announced that the SuperCPU 64/10 (the 10 MHz version) has been cancelled due to insufficient interest in that model. At the same time, there has been an official announcement of a 128 version. This latter decision by CMD was based on the large response from the 128 user community for such a product. But this latter announcement comes with a price: time. In order to make the 128 version feasible, CMP will attempt to co-develop parts of the 128 version along with the present 64 version, which they expect will now be delayed for an additional two months. For further details of these announcements, see this issue's installment of On The Horizon.
EditWhat is the SuperCPU?
The Super64 CPU is an accelerator module that speeds up the operation of your C-64/128 computer. It plugs directly into the cartridge port, and not only gives your computer added speed in calculations, but also provides the computer portion of JiffyDOS (CMD's disk speed enhancement speed). At its heart is the W65C816S microprocessor running at 20 MHz and a CPLD (Complex Programmable Logic Device IC) which contains the custom logic required to mimic the characteristics of the Commodore 64. The C-64 version also contains 128K Bytes of high-speed Static RAM (the same type of high speed cache memory found in 486/Pentium systems), and 64K Bytes of ROM. The 128 version will include additional RAM, ROM and custom logic to allow it to operate in both 64 and 128 modes.
EditPhysical Characteristics
The SuperCPU is contained within an enclosure that measures approximately 6" wide by 3" high and 2"deep.The enclosure has an opening for the Cartridge-Port Pass-Thru connector at the rear, precisely in line with the computer's Cartridge Port. The unit is about the same width as ;I RAMLink or Commodore REU. The main circuit board inside the SuperCPU mounts vertically, keeping the depth of the unit to a minimum. This helps to prevent devices plugged into the pass-thru port from extending too far back from the computer. Three easy-lo-me toggle Mulches line the tipper front edge of the unit: ,i Master Enable/Disable switch, a JiffyDQS Enable/ Disable switch, and a Speed selection switch. While the current prototype lacks a reset button and LED status indicators, these options are being considered for the final design.
EditInstallation
Installing the SuperCPU 64 is simple: just plug it into the Cartridge port. No additional wiring or jumpers need to be installed inside of the computer. (The C-128 version may, however, require a jumper clip.)
EditOperation
Operating the SuperCPU requires no special knowledge. The user can perform ail standard computer tasks in exactly the same manner as with a stock system, gaining the benefit of greatly accelerated speed. The toggle switches on the unit are clearly labeled, easily accessible, and can be used without having to refer to a manual in order to determine their function. As with CMD's RAMLink, the SuperCPU has been designed to work out-of-the-box with any C-64 or 128 computer—no manual "tuning" adjustments will be required.
EditCompatibility
The SuperCPU 64 operates with C-64 and C-64c computers as well as the C-128/128-D in 64 mode. The W6SC816S supports all legal 6502/ 6510/8502 opcodes, and will therefore provide a very high level of compatibility with existing software. The C-64 memory map is emulated exactly by the CPLD, and proprietary write-thru logic in this chip ensures full compatibility with all VIC graphic modes and memory mapping.
REU’s: The CPLD chip in the SuperCPU includes special DMA transfer logic to provide 100% compatibility with all types of data transfers to and from Commodore REU's. The unit does not have to be slowed down to 1 MHz in order to initiate a DMA transfer to/from the REU.
RAMLink: The Super CPU is 100% RAMLink compatible, and contains its own version of RL-DOS, which runs from the SuperCPU's high-speed Static RAM. The faster RL-DOS, along with the efficiency of new 65C81IJS opcodes allows faster data transfers to and from RAMCard memory and also speeds up data transfers to/from CMD HD Series hard drives connected to RAMLink's parallel port.
GEOS: Version 2.0 will be 100% compatible. Special software will be provided with the SuperCPU allowing GEOS to run at full speed.
EditPerformance
To help achieve its high level of performance and to accommodate the 20 MHz speed, all operating system routines are downloaded into 64K of the high-speed Static RAM during power-up. This feature eliminates the bottleneck caused by ROM-based operating system code (on PC's, this technique is called ROM-BIOS shadowing). 64K of high-speed SRAM remains free for programs. In addition, buffered write-thru circuitry (similar to PC cache controllers) eliminates the need to slow down when writing data into computer.
EditAdditional Features
Built-in JiffyDOS Kernal ROM: The computer portion of JiffyDOS is built into the SuperCPU, providing DOS-Wedge commands and enabling high-speed serial transfer rates to and from JiffyDOS-equipped disk drives. The JiffyDOS Enable/Disable switch is designed to function on the fly without disabling the accelerator itself.
Cartridge Port Pass-Thru: Enables the full use of most plug-in hardware devices such as REU's, RAMLink, Swiftlink, SID Cartridge, GEORAM, and some software cartridges. These devices will work while the accelerator is running at 20 MHz.
GEOS Software: Custom software to optimize GEOS operation is provided. Additionally, an intelligent write-thru hardware circuit designed especially for GHOS effectively eliminates major performance bottlenecks associated with previous accelerator designs. Coupled with the 20 MM/, clock speed, this feature will boost the performance of GEOS far beyond anything previously available.
Speed Selection: The speed selection switch provides three options: 1) Slow (1 MHz) mode for compatibility with programs (such as some games) that may operate too quickly in the turbo mode; 2) a"soft" Turbo mode which operates at 20MHz and provides programs with a software speed selection register for switching to Slow speed when necessary; and 3) a "forced" Turbo mode which keeps the CPU in 20 MHz mode regardless of the setting of the software register. This mode is useful for providing compatibility with existing programs that unintentionally alter the software register. (Note: The SuperCPU performs disk access functions properly in all three speed modes.) The user can change speed modes by toggling the speed selection switch while the SuperCPU is operating without quitting from the current program.
EditExpansion Capabilities
The SuperCPU includes an internal connector (called the "Rocket Socket”) which will enable the user to plug in a CMD-supplied HAM Expansion card. This card will have on-board SIMM sockets and can contain from 1 to 16 Megabytes of Dynamic RAM (DRAM). The RAM on this card can be used as either data or program storage. In addition, some or all of this RAM can be configured for use as an ultra-high-speed RAM disk drive.
EditDevelopment Support
CMD will be actively working with developers willing to create new commercial software and/or modify existing software to take full advantage of the SuperCPU. A comprehensive developers package will be available, and will include an assembler which supports all 65C816S opcodes and addressing modes. In addition to the assembler, extensive documentation will provide pertinent technical specifications, guidelines, and sample code. This package will enable developers to produce programs which take advantage of the 65C816S's enhanced instruction set, 16 MB addressing capability (for users with the optional SuperRAM Expansion Card), as well as other SuperCPU capabilities.
EditProgrammable Functions
The SuperCPU contains a special register which allows programmers to control the clock speed. An additional register is used to control the SuperCPU's WriteSmart™ function (see the sidebar), which determines what areas of the SuperCPU memory are mirrored in the host computer. Applications which can use reduced mirroring can significantly increase their overall operating speed.
EditTemporary Conclusion
As mentioned previously, the SuperCPU is a work-in-progress, and it will take a little more time before everything is known, and before everything that appears to be “known” now is really considered to be “carved in stone”. If anything can be concluded, I believe that CMD is creating a powerful new engine to power our C-64’s and 128’s, for those of us who either want or desire that power. Clearly, the features outlined here show that this design goes far beyond other previous accelerators in the areas of performance, expandability, compatibility, and features.
Furthermore, the creation of an assembler and the developer’s kit hints at the possibility of new applications in the future that will take advantage of the power and resources this new device brings to the C-64/128 platform. Naturally, we'll keep you informed as further developments unfold.
EditSome SuperCPU Technical Notes
The SuperCPU operates independently of the host computer's clock, but can synchronize with the host when necessary. This allows the SuperCPU to process data at a full 20 MHz while the VIC chip continues normal operation. Slowdowns can occur, however, because the host computer's memory and I/O locations must be updated when the associated SuperCPU memory locations are changed. In addition, serial bus timing routines must be performed at the standard 1 MHz speed.
Since the host computer's clock and memory operate at a slower speed than the SuperCPU, memory transfers between the two must be synchronized. Such transfers are the result of using LOAD and STORE instructions (such as LDA or STX) when the memory referenced is part of mirrored memory.
By nature of its design, the SuperCPU is able to maintain a minimum effective speed of 4 MHz during these memory transfers. By optimizing code for the SuperCPU, higher transfer rates are possible.
Programmers can also take advantage of the WriteSmart™ and CacheWrite™ features within the SuperCPU to further optimize their code. Doing so allows optimum speed during memory transfers, and avoids transfers when they aren't required. Here's a brief overview of these features.
WriteSmart: This feature determines which areas of SuperCPU memory and host computer memory must be mirrored. A register within the SuperCPU allows setting of four different configurations: all memory, BASIC (for default screen and color memory), GEOS (GEOS screen and color memory), and none. I/O memory is always mirrored unless I/O is switched off.
CacheWrite: This feature works in conjunction with STORE instructions, and holds a byte that needs to be placed into the
host's memory until the host can accept it. If no further STORE instructions occur while the cache is full, no clock-stretching will be required in the SuperCPU, and optimum speed will be maintained.